Alibaba’s XuanTie C950 is a RISC-V server CPU with a self-developed AI acceleration engine, presented as natively supporting large models including Qwen3 and DeepSeek V3 through chip–model co-design. The supplied sources do not substantiate the specific claim that a 64-core C950 runs Qwen3.8-27B at roughly 30 tokens per second, nor do they provide independently verified throughput, power, latency, or efficiency measurements. Independent benchmarking is therefore needed to establish both the claimed speed and whether it is practically competitive with existing local-inference hardware.
Scott already holds the relevant position in `dev:concept.hardware-aware-local-inference` and `ip:concept.capability-audit`: hardware claims must be tested under representative conditions, including throughput, precision, memory pressure, power and practical deployability. The C950 claim still matters because independently validated 27B-class CPU inference on RISC-V could alter his local-inference operating point and strengthen sovereign alternatives to CUDA, but the supplied evidence contains no measurements sufficient to do so yet.
dev:concept.hardware-aware-local-inferenceip:concept.capability-auditip:framework.sovereign-software-assuranceradar:concept.cpu-inferenceradar:concept.inference-efficiencyradar:concept.local-inferenceradar:cpubrrr-laptop-cpu-inference
queries asked of Scott's wikis
- CPU versus GPU local inference economics
- RISC-V and AI hardware sovereignty
- chip-model co-design for LLM inference
- local inference benchmark methodology and tokens per watt
- open-weight models on alternative hardware stacks
- hardware acceleration for agent workloads
2026-08-20T14:36:51Z
Repeated refreshes have produced only discussion churn around already-known benchmark omissions, with no primary artifact or independent measurement. This episode has faded as a standalone lead and can be reopened if reproducible performance, power, or efficiency data appears.
2026-08-19T16:54:57Z
The refreshed comments and engagement remain repetitive amplification of known benchmark gaps; no independent measurement, primary artifact, or implementation has appeared. The C950 result remains an unvalidated single-origin performance claim.
2026-08-19T07:30:27Z
The refreshed comments add no new measurement or artifact and continue to repeat already-known benchmark caveats. The performance and efficiency claim remains a single-origin lead despite interest in the surrounding local-inference topic.
2026-08-19T03:32:43Z
The refreshed comments remain repetitive amplification of already-known benchmark gaps and add no primary artifact, independent measurement, or implementation. The 30 tok/s result is still a single-origin lead, not evidence of practically competitive RISC-V inference.
2026-08-19T02:29:23Z
The refreshed discussion adds no independent benchmark, primary artifact, or implementation evidence and continues to recycle known methodology concerns. The 30 tok/s result remains a single-origin claim awaiting quantization, context, prefill, memory, power, and efficiency measurements.
2026-08-19T01:24:13Z
The latest discussion refresh adds no independent benchmark, primary measurement artifact, or implementation evidence; it only repeats known methodological gaps. The C950 throughput claim remains a single-origin lead awaiting validation.
2026-08-18T23:44:14Z
The refreshed discussion remains repetitive amplification of known benchmark omissions and adds no independent measurement, implementation, or primary artifact. The 30 tok/s claim therefore remains a single-origin lead rather than evidence of competitive RISC-V inference.
2026-08-18T22:37:26Z
The refreshed comments repeat existing benchmark-methodology concerns and add no independent measurement, implementation, or primary artifact. The case remains an unvalidated single-origin performance claim despite broader local-inference interest.
2026-08-18T21:36:07Z
The refreshed discussion adds methodological skepticism—not corroboration—by highlighting missing quantization, context, prefill, memory, and efficiency details. The throughput claim remains a single-origin assertion with no independent benchmark or first-party measurement artifact.
2026-08-18T21:29:59Z
grounded: known/medium — Scott already holds the relevant position in `dev:concept.hardware-aware-local-inference` and `ip:concept.capability-audit`: hardware claims must be tested unde
2026-08-18T21:27:12Z
origin walked (codex/luna, conf 0.93): anchor reddit.post.1vs0wsl -> echo.x.f7ee3c03af by TP Huang (@tphuang)
2026-08-18T21:25:19Z
case created — The reported native execution of a mid-sized open model on new RISC-V silicon is a concrete and consequential inference claim, but currently rests on one secondary report.